Hello!

I’m Yashwant Dubbaka

A rising senior at the University of Michigan, exploring new-grad opportunities in the silicon industry.

Yashwant Dubbaka, Design Verification Engineer

yash_dubbaka.sv

1module yash_d #(2  parameter string3    TECHNOLOGIES =4      "UVM · SystemVerilog · Verilog"5) (6  ddr4_dfi_if.mon ddr4,7  amba_ahb_if.mon ahb8);9endmodule

yash_dubbaka.vcd · 0–50 nsall signals valid

GitHub LinkedIn Resume

01 — About

Background

I care about the part of chip design where you prove something actually works. That means constrained-random environments that find the bugs a directed test would miss, assertions that pin down control-path intent, and formal proofs for the properties that have to hold every cycle — then mining coverage until there is nothing left unexplained but documented waivers.

I work across the stack rather than at one layer of it: a UVM environment for security IP at Qualcomm, a torus NoC characterized across 156 simulations, and a 16-bit RISC-V processor carried from schematic to DRC/LVS-clean layout. The dual degree in business is deliberate — verification is ultimately a schedule-and-risk problem, and it helps to think about it that way.

Relevant coursework

VLSI Design
Computer Architecture
Integrated Circuits
Machine Learning
Networking Systems
Digital Design
Computer Organization
Signals and Systems
Data Structures and Algorithms

Outside the lab

10-year-old me at one of many chess tournaments!

Golden hour on the coast. — 10-year-old me at one of many chess tournaments!

Education

B.S.E. Computer Engineering & B.B.A. (Dual Degree), Minor in Mathematics
University of Michigan, Ann Arbor
2023 — May 2027

02 — Skills

Tools I reach for

Verification

UVM
SVA
Constrained-random stimulus
Functional coverage
Formal property verification
RAL

Languages & Libraries

SystemVerilog
Verilog
Python
C/C++
TCL
Bash

Tools

Verdi
VCS
JasperGold
ChipStack
Claude Code
QuestaSim
CocoTB
Make
Linux/LSF

Protocols

DDR4/DFI
AMBA AHB
On-chip interconnect (NoC)

Custom Design

Cadence Virtuoso
Spectre
Calibre DRC/LVS
ADE

03 — Work

Where I've worked

May 2026 — Aug 2026
Design Verification Engineer Intern · Qualcomm
Santa Clara, CA
Owned verification of an authentication IP from raw RTL through SoC integration sign-off.
- Architected a UVM environment for authentication IP from raw RTL, applying ChipStack agentic generation to boilerplate, and reached regression sign-off for SoC integration in 5 weeks against the team's 15-week manual estimate.
- Authored a verification test plan spanning 14 features and 120+ sub-features of the security architecture, driving an 80+ test suite covering negative stimulus and illegal-access scenarios.
- Closed code and functional coverage by mining regressions for uncovered bins and writing targeted constrained-random sequences, eliminating every coverage hole except documented waivers for unreachable logic.
- Developed 40+ SystemVerilog assertions for control-path behavior and verified AHB protocol compliance with Cadence ABVIP, debugging JasperGold counterexamples until each targeted property reached full proof.
- Owned the bug closure loop with design teams by isolating regression failure signatures to specific RTL logic and filing reproducible testcases, re-qualifying every RTL drop within 48 hours to hold the verification schedule.
- UVM
- SystemVerilog
- JasperGold
- ChipStack
- AHB
Jun 2025 — Aug 2025
Software Engineer Intern · Deloitte
Detroit, MI
- Built a Python ETL pipeline processing 50,000+ threat intelligence records, cutting processing time roughly 60% by replacing row-wise lookups with parameterized SQL existence checks.
- Python
- SQL
- ETL

04 — Projects

Selected work

Torus 4×4 Mesh NoC

Jun 2026 — Present

A 16-router bidirectional torus network-on-chip, verified for deadlock freedom and characterized across 156 simulations to find its saturation point.

Designed a 16-router bidirectional torus NoC in SystemVerilog with deterministic routing, 2 virtual channels, and dateline deadlock avoidance, verifying freedom from deadlock across all traffic patterns.
Built a CocoTB environment with packet scoreboarding, randomized backpressure, and functional coverage, closing 57 tests over 4,608 packets and all valid endpoint pairs.
Characterized throughput and latency across 156 simulations sweeping FIFO depth, offered load, and traffic pattern, identifying depth-4 buffering as the saturation knee.

SystemVerilog
CocoTB
Python
IVerilog

4,608
Packets verified: 156
Sims swept

drag to rotate · x wraps around the ring · y around the tube

Traffic pattern

Every node equally likely — the baseline for load sweeps.

Route: R0 (0,0) → R3 (3,0)
Algorithm: torus DOR, X→Y
Output ports: WEST
Hops: 1 / 4 max
Dateline: crossed 1×
Virtual channel: VC0 → VC1 (held)

source
destination
VC0
VC1 (post-dateline)

Four flits per packet — wormhole flow control keeps one packet spread across several routers at once. Click any router to inject from it.

RISC-V 16-bit Processor

Jan 2026 — May 2026

A full custom-CMOS 16-bit RISC-V processor taken from schematic through physical layout and DRC/LVS clean signoff.

Designed a 16-bit RISC-V processor integrating decoder, register file, ALU, shifter, memory, and a branch-capable PC.
Implemented a radix-2 Kogge-Stone ALU adder in Cadence, reducing carry propagation from O(N) to O(log N).
Optimized sizing and speed paths with Spectre simulations, reducing ALU rise delay from 467 ps to 132 ps.
Completed CMOS physical layout with port planning, metal routing, and Calibre DRC/LVS verification, reducing adder area 32% while managing interconnect length, capacitance, and high-fanout routing constraints.

Cadence Virtuoso
Spectre
Calibre
Verilog
APR

3.5×
Faster ALU: −32%
Adder area

Datapath · active path per instructionADD R3, R12 → R12 + R3 → R12

Both operands come from the register file: Q_a drives ALU B, Q_b drives ALU A, and the result writes back to Rdest.

16-bit radix-2 Kogge-Stone adderStage 1 — span 1

Prefix cells: 49
Carry depth: 4 = log₂(16)
Ripple-carry depth: 16

Each stage merges group generate/propagate pairs across twice the span of the last, so every carry resolves in four levels instead of sixteen. Click any bit to trace the cone of cells feeding its carry.

DDR4 Memory Subsystem

May 2025 — Aug 2025

A dual-agent UVM environment for a DDR4 memory controller, checking DFI protocol timing across the controller FSM.

Architected a UVM environment for a DDR4 memory controller with dual-agent architecture and scoreboard, validating data integrity across 65,000+ memory locations.
Implemented SystemVerilog assertions and a reference model checking DFI protocol timing across a 6-state controller FSM, closing functional coverage over 10+ scenarios.

SystemVerilog
UVM
QuestaSim
DFI

65k+
Locations validated

05 — Contact

Reach me here.

yrdubbaka@gmail.com